Data Transmission in the Fast Lane

Advanced signal conditioning and error correction have contributed to achieving channel bandwidth far beyond what was expected just a few years ago. Moving to a higher order modulation provides a pathway to achieving next generation speeds.

Constantly increasing data transmission speed over a communication link has been a key enabler of achieving higher computing performance since the 1980s. Faster data transmission and processing delivers more information in less time while increasing efficiency. The connector industry has been a key contributor to this transformation as discrete bundles of wires soldered to single-sided edge connectors were upgraded to high-speed, high-density backplane connectors designed to support controlled impedance differential pair signaling.

Bandwidth is the maximum possible data transfer rate or capacity of a channel in a given period of time and is typically expressed as bits per second. Similar to a water pipe, the bigger the pipe (bandwidth), the greater the capacity to deliver water (data). Users of technology that range from consumers playing video games to operators of massive artificial intelligence data centers expect system bandwidth that can support data intensive workloads.

Major I/O standards-writing organizations have recognized the necessity of being capable of supporting increased bandwidth demand and have published roadmaps to higher throughput. The PCIe Special Interest Group (SIG) announced the PCIe 7.0 specification on June 11, 2025, with a bandwidth of 128.0 GT/s. PCIe measures performance in terms of gigatransfers per second (GT/s), which is similar to gigabits per second except GT/s includes both data and overhead. The PCIe 8.0 specification is expected to reach 256.0 GT/s via a x16 configuration and is planned for release by 2028.

The Ethernet Alliance has been particularly aggressive in anticipating future data transmission speed requirements and for the past decade has annually published a roadmap to assure users that Ethernet will be capable of supporting next generation equipment.

There is little reason to believe the race to increase bandwidth will slow anytime in the foreseeable future. With 112 Gb/s per lane becoming the current standard for Ethernet per IEEE 802.3ck and OIF CEI-112G, the next leap — to achieve 224G lanes — is currently in early adoption.

Pathways to achieving next generation speeds

A traditional solution to increasing channel data throughput is to combine data streams of multiple lower speed lanes. For example, the PCIe specification defines a user choice of 1, 2, 4, 8, or 16 lanes, each running at 2.5, 5, 8, 16, 32, 64, or 128 Gb/s. This multi-lane approach works well but results in a higher number of low-speed lanes at the I/O port. The PCIe specification defines a family of high-density edge connectors offered in six different contact counts.

Advanced signal conditioning and error correction have contributed to achieving channel bandwidth far beyond what was expected just a few years ago.

The ability to transmit 224+ Gbs of information on a single differential pair is very attractive where I/O port density is an issue. Moving to a higher order modulation provides a pathway to achieving next generation speeds.

Industry designers quickly evolved from Non-return to Zero (NRZ) modulation to PAM4 signaling, which delivers two bits of information per symbol instead of one, effectively doubling the throughput (efficiency) for a given bandwidth.

A current debate within the industry is revolving around the need to adopt a higher order modulation such as PAM6 or PAM8, both of which will increase data throughput while introducing design challenges including sensitivity to noise, and lower signal-to-noise ratio.

Another option requires a transition from copper to fiber optic channels. High-speed copper links suffer from multiple challenges that increase with speed.

1. Signal integrity and channel loss. (This requires advanced equalization and error correction, and will ultimately limit channel reach capable of supporting design requirements.)
2. Reduced channel length.
3. Increased power consumption and heat generation.
4. Reduced manufacturing tolerances and resulting production yield. (This impacts price.)

Data transmission over optical channels offers much greater bandwidth and reach without the loss and signal distortion inherent in copper channels.

New high-speed benchmarks

Standards writing organizations are rushing to stay ahead of immediate industry demands. IEEE is expected to release the P802.3dj Ethernet standard in late 2026 to support 212 Gb/s lane speeds. This standard is expected to provide a gateway to 1.6 and 3.2 Tb/s aggregate links.

This month, the Ethernet Alliance will host a high-speed networking plugfest to demonstrate interoperability and compliance testing at rates ranging from 200 Gigabit Ethernet to 1.6 Terabit Ethernet. Testing will encompass a wide range of interconnects, including copper cables, as well as optical based transceivers active optical cables, retimed optics, and linear optics.

In addition to the performance and packaging density advantages offered by fiber optic interconnects, optical implementations such as co-packaged optics are now seen as a path to reducing power consumption and a roadmap to supporting future generations of high-performance computing equipment.

Component suppliers are responding quickly to the availability of 200G/lane connectivity with many products shown at OFC 2025 (see my review of the show). Incredible demand for AI computer clusters is expected to replace current 100 Gb/s links with rapid adoption of 200G/lane optics in 800G and 1.6T transceivers. Broadcom has already introduced a family of 200G/lane optical digital signal processors.

An emerging category of silicon photonic integrated circuits (PICs) are chip level devices consisting of integrated waveguides, lasers, modulators, and detectors that bridge the gap between electrical and optical functions.

Acacia introduced the company’s new silicon photonics optical engine product family designed to support AI infrastructure with 200G/lane capabilities.

The Keysight booth at OFC 2025 demonstrated equipment designed to test validate and simulate 200G/lane channels. 200 Gb/s lanes represent the next immediate step in the constantly increasing cycle of performance upgrades.

Adoption of parallel multi-lane transmission, advanced modulation and conversion to optical signaling are not the only options available to designers.  Multicarrier NRZ transmission divides a high-rate data stream into several parallel lower-rate subcarriers to achieve higher aggregate bandwidth. Optical channels can be multiplexed by applying polarization or wavelength techniques. The use of multicore optical fiber increases the capacity of an optical cable.

Work has already begun on exploring 448G per lane speeds and the hardware required to support it. A recent white paper published by Keysight discussed the technical and practical challenges involved in achieving 448 Gb/s transmission. Feasibility of 448G/lane channels was demonstrated balancing the effects of PAM, 4, 6, and 8 modulations with resulting signal to noise ratios.

Scaling interconnect speeds to 3.5T (448 Gb/s X 8 lanes) is crucial for meeting the performance demands and avoiding data bottlenecks of future AI clusters. Laboratory tests have demonstrated the ability to improve signal integrity at these speeds using optimized components, short interconnects, advanced equalization and coding. Achieving this level of performance in high volume production will pose a challenge to system designers, and component suppliers including the high-performance connector industry.

Visit Bob Hult’s Connector Supplier archive for more high-speed coverage, his Tech Trends series, and show reports.

Like this article? Check out our other Fiber Optics and High-Speed articles, our Datacom Market Page, and our 2025 Article Archive. 

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