PCIe High-Speed Interface Offers a Flexible Future

By Contributed Article | September 02, 2025

The PCI standard continues to evolve to meet the challenges of PCB design and offers the flexibility to play a role in future high-speed applications.

By Florian Guglhör and Martin Adamczyk, ept connectors GmbH

The PCI (Peripheral Component Interconnect) standard originated in the early 1990s as a bus protocol for chip-to-chip communication and the connection of external peripheral devices. In the years since, data communication and system design has changed dramatically, but PCI has evolved and adapted too, and its flexibility has enabled it to remain in widespread use in high-end graphics cards, servers, and embedded systems.

In the early 2000s, PCI became PCI Express (PCIe) and a new era in data transmission began. While PCI 2.2 was comparatively limited with a maximum of 133 MB/s, PCIe 6.0 theoretically allows up to 64 GB/s in the (x8) configuration, an almost thousand-fold increase. The high-speed bandwidth of PCIe protocols doubles approximately every three years. PCIe technology transfer ranges support server applications for artificial intelligence, autonomous driving, embedded applications, and industrial automation.

From PCI using (x8) lane configuration. (Image: ept GmbH)

This enormous development is particularly evident in data-intensive fields of application such as artificial intelligence, autonomous driving, and high-performance computing. While PCIe 5.0 systems in data centers currently already enable 32 Gb/s, PCIe 3.0 applications with 8 Gb/s are still mainly used in the traditional embedded market. The first PCIe 4.0 modules are only just being introduced, but the broader market launch is not expected for about another five years. PCIe 4.0 protocols are currently used for control systems for semi-automated driving in accordance with SEA Level 3, while the PCIe 5.0 system is required for fully automated driving in accordance with Level 4 and 5.

PCIe generations and their bandwidths

PCIe is ahead of its time, by design

PCIe is modular and can be adapted to future requirements. In fact, PCIe interfaces often progress much faster than their actual use. This helps manufacturers future-proof designs, with the expectation that an interface will perform for years to come. Additionally, future-looking design may include advances in material and manufacturing techniques that allow continuously higher data rates.

However, there are challenges to anticipating the future. New high-speed applications require systems to process twice as much data, without increasing installation space. This inevitably leads to increasingly complex designs. The miniaturization of individual components in turn leads to higher prices. As data rates increase, so do the requirements for physical signal routing. High-frequency signals over 16 Gb/s (e.g., PCIe 4.0) require complex PCB designs with multiple layers, special materials, and precisely controlled impedance. Micro vias, special dielectrics, and high-density interconnects (HDI) also increase manufacturing costs.

Planning for 25 Gb/s Ethernet on COM Express

Despite sufficient bandwidth through PCIe 4.0 (16 Gb/s per lane), the implementation of 25 Gb/s Ethernet on COM Express (Computer on Module) is not yet fully realized. The main reasons include a lack of integration of 25 Gb/s Ethernet controllers in COM modules; insufficient driver and firmware support; and limited signal quality due to existing components and incompatible cable and connector systems. Another bottleneck is the physical space on the PCB. Applications with up to 400 signals, such as FPGAs or COM Express modules, require complex multilayer routing (often 10-16 layers), controlled impedance, differential pairs, and an EMC-optimized layout. The miniaturization of such systems further exacerbates this problem.

Higher frequencies also lead to stronger electromagnetic emissions. In highly integrated designs with narrow signal spacing, reflections, crosstalk, and interference occur, which requires robust shielding concepts and ground routing.

High-speed connectors offer optimum data transport

Classic design approaches are reaching their limits in modern PCIe applications. Innovative connection solutions that enable high data rates in a reliable, space-saving, and cost-optimized manner are particularly in demand in the embedded sector. The new Colibri interface is one solution that offers adaptability through three variations:

– 10+ For COM Express modules according to revision 2.1
– 16+ For COM Express modules according to revision 3.1
– 25+ For COM Express modules according to revision 3.1 and 25 Gb/s Ethernet applications

The insertion loss limit for a connector for PCIe 4.0 applications is – 1.8 dB at a frequency of 8 GHz.

Insertion loss of the three variants: 10+, 16+ and 25+ Gb/s (Image: ept GmbH)

The Colibri 25+ connector exceeds the PCIe requirements, so losses in the high-speed design of the cost-optimized PCB can be compensated by the connector. It is a less expensive solution for PCB design due to optimized layout structure. It supports 25 Gb/s Ethernet for the first time on COM Express, offering miniaturization and EMC optimization through integrated shielding, and is future-proof for PCIe 4.0 applications. This solution enables reliable and scalable signal transmission in board-to-board applications, even where space is limited, at high data rates, making it an important basis for the next generation of modular embedded systems and applications in PCI interfaces.

Signal transmission Colibri (Image: ept GmbH)

Looking to the future, autonomous technologies such as 5G connectivity, autonomous driving, cybersecurity, V2X communication, edge computing, and blockchain technology will have a significant impact on data transfer. The latest generation of interconnect solutions is ready to serve today’s high-speed needs as well as those that are coming in the near future.

To learn more about high-speed interconnect solutions, visit ept GmbH.