DesignCon 2018 in Review
The industry continues to take impressive steps forward, as evidenced by new products in the connector and cable world.
DesignCon 2018 opened under sunny Bay Area skies, which seemed a perfect match for the mood among attendees. This conference featured over 100 technical sessions organized in 14 conference tracks, along with a two-day exhibition with 175 vendors that demonstrated their latest hardware and software. DesignCon continues to be the go-to conference for bleeding-edge chip, board, and system design engineers. Many of the technical sessions were standing-room only and addressed topics that ranged from measuring signal integrity in high-speed PAM4 channels to advanced modeling and simulation techniques. DesignCon is unique in that over 32 connector and cable assembly manufacturers chose to participate in this expo, at least seven more than last year.
DesignCon never fails to amaze by illustrating how much progress can occur over one short year. Those engineers who persist in predicting the imminent demise of copper in high-speed channels will continue to be frustrated as a combination of highly refined connectors, optimized PCB footprints, and state-of-the art SerDes devices continue to keep copper channels the most cost-effective choice. Last year, the buzz on the exhibit floor was the emerging ability to achieve 56Gb/s channels utilizing PAM4 signaling technology.
This year, multiple connector suppliers had live demonstrations of 56Gb NRZ and 112Gb/s PAM4 channels. At least one supplier stated that they believe 112Gb/s NRZ channels are possible in the near future. At this point, there are few to no production applications that actually require 56Gb channels, but connector suppliers want to assure system designers that there is a clear migration path to support multiple generations of devices without a wholesale change of interconnects.
Significant advances were evident in board-to-board, backplane/mezzanine, as well as I/O cable interconnects. Utilizing copper twinaxial cable assemblies both inside and outside the box was a major theme.
Years ago, Samtec introduced the concept of using twinax copper or fiber optic cable to “fly over” the PCB in order to avoid the attenuation and noise associated with running high-speed signals through copper traces in a printed circuit board. They should have copyrighted the term, as it was being used all over the exhibit floor.
Samtec continues to introduce new high-speed/density connectors to extend the concept, while the Sliver connector from TE, the ExaMAX IO connector from Amphenol ICC, and the new NearStack Twinax system, along with the BiPass I/O from Molex, provide additional alternatives to routing traces on a PCB. Several of these interfaces are rated up to 112Gb/s PAM4.
The alphabet soup of external pluggable I/O connectors continues to expand with SFP, MicroQSFP, QSFP-DD, and OSFP competing in the market. Nearly every major cable assembly supplier now offers each flavor as they wait to see which will be the long-term volume winner.
In addition to the latest iterations of SFP and QSFP connectors, Yamaichi Electronics displayed their extensive line of copper and optical I/O, including CFP4, CFP2-64, CFP4-64, and CFP8. At the other end of the spectrum, I-PEX displayed their extensive line of separable micro-coax and FPC connectors with contact centerlines as small as 0.35mm yet rated up to 20Gb/s per lane.
Active copper and optical cables assemblies are becoming an attractive option as the industry moves toward 400Gb/s applications. The use of copper cables in high-speed I/O applications creates some problems when increasing data rates mandate larger gauge conductors while the centerlines of high-density connectors continue to shrink. Utilizing their unique signal conditioning chipsets, Spectra7 showed Micro QSFP, QSFP-DD, and OSFP cables that perform to 25Gb/s PAM4 with conductors as small as #36 gauge. Amphenol and FIT indicated that they have begun partnering with Spectra7 to incorporate Spectra7 “GaugeChanger” chips into their cable assemblies. The result is reduced cable bulk and longer reach.
Standards are playing an increasing prominent role in new system architecture. Formal industry standards such as Ethernet continue to push out their technology roadmap to 800Gb/s. More recently, industry consortiums and special-interest groups such as Open Compute have begun having a significant influence on next- generation system design. Several connector manufacturers expressed concern that systems built around what could become generic components with reduced margins would also distribute critical interconnect intellectual property to low-cost suppliers. The Open 19 foundation takes a somewhat different approach by defining only the mechanical dimensions of the mating interface and its location on the box, leaving the door open to supplier innovation for improvement. Open 19 displayed a large server stack utilizing a Molex cable assembly.
Several discussions involved the status of PCIe and emerging competitive standards. PCIe 4.0 was released in late 2017 after what many consider an exceptionally long development cycle. That delay has created opportunities for new competitive protocols to fill the void. Although not physically backward compatible with existing PCIe infrastructure, the Gen-Z open systems interconnect offers advantages of packaging density and low latency with bandwidth that is scalable from 2.5GT/s NRZ to 112GT/s PAM 4 signaling. A modified card-edge version of the 0.6mm pitch Sliver connector from TE Connectivity sporting 8, 16, and 32 differential pairs is defined as the separable interface.
Some of the new products that were released and/or demonstrated at DesignCon this year include:
Amphenol ICC featured an extensive display of their product mix, from legacy to leading edge.
The Cool Edge line has been expanded to include a 1.0mm PCIe version, a 0.65mm Slim Cool Edge configuration with a power contact rating of 3A, and the high-speed 0.60mm Mini Cool Edge that rated to 56Gb/s PAM4.
A live demonstration of the Paladin backplane connector verified performance to 112Gb/s PAM4.
Amphenol continues to find applications for their Leap On-Board optical transceiver where reach is less than 100 meters. Finisar was mentioned as a source of an electrically and footprint-compatible second source.
Demand for low profile, high-speed stacking connectors resulted in the introduction of the Chameleon family, which features 6mm and 10mm stack heights and from 40 to 500+ BGA contacts with high-speed performance to 25Gb/s. Design flexibility includes an option for a dedicated power segment.
Higher stack height applications are addressed by the Hirose IT-8 three piece mezzanine connector that is rated to 56Gb/s PAM4.
The Molex booth featured multiple live demonstrations, including 56Gb/s NRZ over a one meter QSFP-DD cable assembly, an Impulse Orthogonal Direct interface running at 112Gb/s PAM4, a BiPass cable assembly running at 56 Gb/s PAM4, as well as a new NearStack twinax cable jumper running at 56Gb/s NRZ.
Molex also introduced their new Mirror Mezz mezzanine connector. Its hermaphroditic design provides assembly savings while delivering up to 56Gb/s NRZ performance.
Samtec continues its tradition of extending performance of board-to-board connectors with the introduction of their NOVARAY family, which is rated to 56Gb/s NRZ / 112 Gb/s PAM4.
Samtec introduced the Ultra-Dense AcceleRate HD family of board-to-board connectors, which is a four row, 5mm stack height surface-mount connector rated to 56Gb/s PAM 4. The cable-to-board version using their low skew Eye Speed cable is an addition to their families of flyover products.
Emphasizing their continuing expansion into the high-speed backplane market, a live demonstration of an ExaMAX backplane connector test board was running four ports at 56Gb/s PAM4 over 30” of PCB trace.
A large model rack illustrated the many copper and fiber system packaging options offered by Samtec.
The TE Connectivity booth featured the expanding variety of the Sliver 2.0 connector now rated to 56Gb/s PAM4. Adaptations of this versatile interface have been adopted by multiple consortia, including COBO, Gen-Z, and the Open Compute Project. A live demonstration of a Sliver to QSFP over 4 meters of cable was running at 56Gb/s PAM4. Another demonstration featured the STRADA Whisper backplane connector successfully running at 112Gb/s PAM4, with the next possible step of 112Gb/s NRZ in a cable backplane assembly.
TE continues to innovate and refine to differentiate among industry standard interfaces. Recognizing that thermal management is a major design issue, TE showed a rack simulator with a front panel fully populated with MicroQSFP connectors conducting 12.8TB of data. Rather than traditional front-to-back cooling, the connectors utilized a modified heat spreader on the cage assembly to allow side-to-side cooling.
Cable backplanes were promoted at the Amphenol, Molex, and TE Connectivity booths, but suppliers are emphasizing their full range of configurations, including backplane, midplane, orthogonal midplane, orthogonal direct, and cable. Cable backplanes remain a more expensive option, but have found a niche market in large systems where channel reach requirements are exceptionally long. In the short term, orthogonal direct midplane architecture appears to offer an attractive balance between electrical and mechanical performance in high-end systems.
The critical role that advanced SerDes plays in achieving ever-increasing data rates was evident, as many booth demonstrations credited Xilinx and Credo silicon.
Representatives of leading connector manufacturers expressed an impressive degree of optimism as they announced a number of advanced products that feature greater signal integrity, faster data rates, higher signal density, and better thermal performance. Product development is at record levels, with many new interfaces in the design pipeline. Fiber optic alternatives will be adopted in select applications, especially those that require long reach, high-bandwidth, and reduced size and weight, but the final choice of media comes down to cost per bit performance that meets system specifications.
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