In the Blink of An Eye, From PCIe 7.0 to 8.0

The PCIe 7.0 specification was released in 2025, with speeds of 128 Gigatransfers per second, doubling the maximum rate of PCIe 6.0. PCI-SIG promises to double bandwidth every three years, and last month’s preliminary 8.0 draft release shows that progress is accelerating to meet the high-speed needs of the AI era.

In June 2025, PCI-SIG released the PCIe 7.0 specification to its member companies, a group that includes semiconductor companies, OEMs in every technology category, interconnect manufacturers, and data center hyperscalers, playing a critical role as artificial intelligence and machine learning training systems become a key driver of cloud computing workloads. PCI-SIG’s roadmap promises to double bandwidth every three years, an intense pace that means right on the heels of the PCIe 7.0 announcement, work has already begun on PCIe 8.0.

PCIe 7.0 delivers a raw bit rate of 128.0 GT/s, double the 64.0 GT/s of PCIe 6.0, and up to 512 GB/s of bi-directional throughput in a full x16 lane configuration. The specification uses PAM4 (Pulse Amplitude Modulation with 4 levels) signaling and a FLIT-based encoding scheme, first introduced in PCIe 6.0, that encodes data in fixed-size flow control units rather than packets. This combination allows bandwidth to double without doubling the Nyquist frequency, which extends copper-based physical layer design — for now. Improved power efficiency and full backwards compatibility with prior PCIe generations are other essential features.

The PCIe 8.0 draft, available to members in February 2026, promises to double the performance of PCIe. With an expected release date of 2028, this intense timeline, combined with the approaching limits of copper, puts pressure on connector manufacturers to design a new generation of connectors and cables that can reliably deliver on these speeds while managing crosstalk, interference, and signal integrity. PCIe 6.0 interconnect products have only recently entered the marketplace. The needs of data centers and emerging quantum computing interconnects forces the industry into a continual mode of forward-looking development. Critically, early reports indicate that PCIe 8.0 may require a new connector form factor rather than a redesign of an existing generation.

Samtec and Amphenol, PCI-SIG member companies, are entering the market with generation 7.0 products even as their development teams turn their attention to the requirements of 8.0.  Samtec’s signal integrity specialists, system architects, and technical experts contribute to PCI-SIG technical working groups (TWGs) on an ongoing basis.  “Our SI team has advised the PCI-SIG Electrical Working Group (EWG) on system architectural trends based on XPU scale-up and scale-out,” said Matt Burns, Samtec’s director of technical marketing. “Additionally, we expect PCIe 8.0 to continue to use integrated compliance methodologies that Samtec helps to develop and implement within the appropriate PCI-SIG TWGs.”

Burns says work is focused on two key areas. “One, next-gen PCB design reaches for lower loss and reduced reflections, even beyond existing 224 Gbps PAM4 requirements. Hyper-optimization of vias, including anti-pad and back-drill dimensions, will be key. Implementing PCIe 8.0 in near-chip applications will be tricky, so we can expect to see co-packaged PCIe 8.0 implementations, as we have with 224 Gbps PAM4 use cases. This design approach bypasses core and BGA package effects and reduces interconnect loss by up to 5 dB,” he said.

“Two, when it comes to testing PCIe implementations, test fixture bandwidth requirements for device validation jump from a Nyquist frequency of 32 GHz for PCIe 7.0 up to 64 GHz for PCIe 8.0.  Why is this a challenge? Good SI design practice for test fixtures targets a bandwidth 1.5x the Nyquist frequency.  For PCIe 7.0 test fixtures, this means 2.40 mm RF connectors, cables, and instrument front-end operating up to 50 GHz perform well. New PCIe 8.0 test fixtures will require 96 GHz functionality and necessitate 1.00 mm RF connectors, cables, and instrument front-ends. The raw symbol rate doubling effectively skips over 67 GHz 1.85 mm RF connectors, cables, and instrument front-end from traditional test fixture consideration.”

At OFC 2025, Samtec demonstrated six different systems, all running at PCIe 7.0. Combinations included high-density, high performance mezzanine connector sets with NovaRay^® and AcceleRate^®. Mid-board-to-backplane and mid-board-to-front-panel setups featured Samtec Flyover^® cable systems. Products to support the PCIe 7.0 generation are just entering the market, even as manufacturers turn their attention to the requirements of 8.0.

Samtec’s NovaRay® I/O is PCIOe 7.0 capable, with the highest aggregate data rate on the market at 4,096 Gbps PAM4, with a high-density cable-to-cable bulkhead or threaded 38999 panel connection.

As each generation sets a new benchmark for high-speed computing, the entire connector industry must calibrate its pace of innovation. “PCIe requirements are part of our requests very often. We do not offer protocol-specific BtB connections but our focus remains on high‑speed board‑to‑board interconnects within our FINEPITCH portfolio,” said Thomas Schulze, Group Leader, Board-to-Board Connectors, at Phoenix Contact. “The FS 0.635, FP 0.8, and FR 1.27 series support demanding differential signaling with data‑rate capabilities from up to 30 Gbps (FS 0.635) to 52 Gbps (FP 0.8), depending on configuration.”

Phoenix Contact’s FINEPITCH portfolio provides device manufacturers ideal solutions for PCB connections for industrial requirements.

Phoenix Contact does not manufacture the PCIe card‑edge interface, but its corresponding protocol-specified BtB connectors are frequently used in systems where PCIe‑level signal integrity is required. Features such as shielding in FP 0.8, floating tolerance compensation in FS 0.635, and robust double‑contact designs in FR 1.27 help ensure reliable high‑speed transmission and mechanical stability.

“As PCIe 8.0 pushes channel requirements further, designers should focus on stricter SI control—minimized loss, controlled impedance, and reduced crosstalk. Our simulation support (S‑parameters, TDR, crosstalk) helps customers optimize internal high‑speed links accordingly with our portfolio. We continue to refine our connector technologies in line with the increasing demands of next‑generation high‑speed applications and remain available for deeper technical discussions or simulation support.”

Connector and cable products that support the requirements of PCIe 6.0 and PCIe 7.0 are beginning to enter the market from PCI-SIG member companies. Look for more in the months ahead.

Tarng Yu Enterprise’s cable solutions for PCIe connectors feature a soldered design that eliminates the need for a paddle card. This direct wiring strategy preserves signal integrity.

Amphenol’s Mini Cool Edge IO features a 0.60mm pitch and a slim form factor design, and is capable of transmitting high-speed signals of up to 128G PAM4/PCIe Gen 7. It allows for significantly longer signal path lengths while maintaining superior signal integrity.

Molex NextStream connector enables data centers to upgrade and meet the demands of data-intensive applications like AI, NVMe-EDSFF storage, CXL, UPI systems and high-performance computing.

To learn more about the companies mentioned in this article, visit the Preferred Supplier pages for Amphenol Communications Solutions, Molex, Samtec Inc., and Tarng Yu Enterprise.

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