Advanced Packaging and Silicon Photonics Extend Moore’s Law

By Robert Hult | June 18, 2024

Approaching the physical limits of traditional silicon chip technology, many predicted we would soon witness the death of Moore’s law. Multi-chip advanced packaging and the rise of silicon photonics offer a path to resuscitation.

Not long ago, the consensus among many engineers was that the practical limits of shrinking semiconductor chip features had been reached, effectively ending Moore’s law, which has been the guiding light of the computing industry for nearly 60 years. Doubling the number of transistors on each chip every two years enabled dramatic increases in computing power, while reducing power consumption and cost.

Advanced chips today may feature billions of transistors with spacing of 5 nanometers or less. The cost of reducing these features by a few nanometers offers diminishing returns on billions of dollars spent on next generation design and process equipment. The cost of building a state-of-the-art chip fabrication plant can run to $20+ billion.

Recognizing the critical importance of semiconductor leadership and implications for national security, the CHIPS for America program is providing up to $54 billion in subsidies to fund research in design, and fabrication of advanced semiconductors. The imperative to stay competitive in advanced chip technology has spread as China, Korea, and Japan have committed billions in subsidies and grants. The European Semiconductor Regions Alliance was created in 2023 to boost the local semiconductor supply chain. The fact that the most advanced chips today are being manufactured exclusively in Taiwan, a country being threatened by China, has provided additional incentive to regain domestic leadership in this critical technology.

The chip industry continued to evolve design and fabrication technologies that have increased performance and density by moving from planar to advanced 3D architecture.

Planar semiconductor technology has been in use since 1959 and is the simplest option to design and fabricate chips.

With every successive manufacturing node, scaling transistor performance becomes more difficult and expensive.

FinFET (fin field effect transistor) devices feature significantly faster switching times and higher current density. It is a 3D structure that has become the basis of modern semiconductor fabrication.

GaA or NanoSheet FET gate-all-around transistors utilize stacked elements and will be used in 3 nm and smaller geometries.

In this chip architecture the gate surrounds all four faces of the channel, which enables greater control of current flow, resulting in high power efficiency.

CFET devices are expected to reach commercial application in seven to 10 years.

The latest developmental refinement of gate-all-around architecture is the complementary field-effect transistor (CFET) which stacks both n- and p-type devices on top of each other to provide improved electrostatic control as well as higher transistor density.

Using these building blocks, integrated circuits (ICs) consist of multiple interconnected electronic components such as transistors, resistors, inductors, and capacitors fabricated on a single silicon die. The result is the ability to fabricate complete systems in high volume and low cost.

Despite continuous improvements in feature density, the process of shrinking transistor dimensions has approached the physical limits of traditional silicon chip technology encouraging some to predict the death of Moore’s law.

Development of multi-chip packaging and the rise of silicon photonics is offering a path to resuscitation.

Rather than fabricating multiple functions on individual chips, the multi-chip module integrates multiple chips and related passive devices on a unified substrate to create a modular subsystem.

The ability to assemble the module using a variety of chips allows designers to create custom low-cost modules that can support very specific applications.

The next logical step was to package subassemblies vertically to conserve space and increase design flexibility. Unlike system on chip (SoC) which integrates multiple functions on the same die, stacked 3D, or system in package, (SiP) bundles multiple “chiplets” on a common substrate.

Each chiplet may have a different function and can include both passive and active devices. Through-silicon via (tsv) technology is used to provide vertical interconnection between chips.

Chiplet architecture that optimizes yield, power efficiency and cost is being widely adopted. Chiplets also support the trend to heterogeneous integration in system design which can include diverse functions such as memory, processors, and opto-electronics.

Co-packaged optics architectures utilize a series of chiplet optical transceivers mounted on the same substrate as an ASIC.

The next wave in system packaging will be driven by advances in silicon photonics.

Silicon photonics (SiPh) is a material platform which enables the creation of photonic integrated circuits (PICs) directly on wafers of silicon. This technology offers advantages of higher speed/bandwidth density, longer reach, reduced latency, and energy efficiency. Fabrication of SiPh circuits is compatible with CMOS standard high-volume processes, which allows PICs to be manufactured using existing foundry infrastructure. 

The ability to integrate conventional CMOS circuits on the same die as photonic elements including lasers, modulators, and photodetectors linked by optical waveguides opens a new universe of system packaging options.

Photonic integrated circuits have already become a key component in advanced pluggable optical transceivers.

Intel has been actively developing its family of Optical Compute Interconnects. These devices will include light sources, modulators, photodetectors, and structures that amplify and guide light.

Using stacked chip technology, Intel demonstrated its developmental low-power OCI chiplet at OFC 24.

Coupled with a CPU in the same package, the link transmitted at 112 Gb/s over a length of optical fibers using eight wavelengths and consuming only 5 pj/bit. Intel anticipates the ability to integrate a pluggable optical connector in the future.

The unprecedented growth of data intensive computing demands, particularly from AI workloads and machine learning, will make the performance and cost advantages of integrated silicon photonics a necessity.  Applications in rack-to-rack, as well as external data center communication, have stimulated development in silicon photonic technology to produce highly scalable optical interconnect solutions. LightCounting recently forecast the sales of silicon photonic chips will reach $3 billion by 2029. Design of next-generation equipment will be enabled by the use of a single technology manufacturing platform to create end-to-end optical connectivity and eventually computation, continuing the spirit of Moore’s law.

The chip industry continued to evolve design and fabrication technologies that have increased performance and density by moving from planar to advanced 3D architecture.

Read about the history of computing and see more high-speed reporting from Bob Hult in his archives.

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Robert Hult
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